1. Field of the Invention
This invention is directed to integrated circuits and more specifically to the input registers associated with static random access memory, dynamic random access memory, and logic integrated circuits.
2. Description of the Prior Art
Static random access memory (SRAM) is well known as a volatile type of memory. In the past, SRAM typically had an asynchronous architecture, i.e., at any one time when a new set of memory addresses is supplied to the SRAM, the information stored in the SRAM memory cells appears at the output after a finite (access) time has elapsed. However, the increased speed of central processor units associated with computers which typically use SRAM has generated a need for high speed SRAM.
One well known way to increase effective SRAM speed in a system is to incorporate registers at the address lines, control lines, and data lines of the SRAM memory cell array input, and/or at the data output line of the SRAM memory cell array.
An SRAM chip is shown in a block diagram in FIG. 1, including the actual memory cell RAM array 10 (here depicted as a 16K.times.4 cell array) having an associated Data In register 12, an Address register 14, and a Data Out register 16. There are 14 address bits A0 through A13 and four data in bits DI0 through DI3, with the corresponding four data out bits DO0 through DO3. The other elements are conventional. This particular block diagram is of the Cypress Semiconductor CY7C158 SRAM chip. This is a fully registered (pipelined) high performance SRAM organized with 16,384 words by 4 bits. The asynchronous output enable signal OE is provided to control the three state data outputs.
The operation of such SRAM chips is completely synchronous, with the exception of the OE signal. All data, address and control signals are sampled on each low-to-high transition of the clock signal. When signal CE is LOW during this transition, the device is selected for operation. The type of operation is determined by the state of the WE signal during this same transition. Signal WE LOW causes a write operation, while WE HIGH causes a read operation. The Data Input and Data Output as well as Address register are also loaded on each low-to-high transition of the clock. The outputs, however, are not available until the next cycle after the address is loaded on the current cycle. The state of the outputs is controlled by the pipeline signals CE and WE and data from the previous cycle and the state of the OE signal.
An SRAM such as that shown in FIG. 1 with integrated registers has the clock line CLOCK provided to the chip, and most of the other input and output lines as shown timed against the signals on the clock line. In this case the clock line is connected to the Address register 14, Data In register 12, Data Out register 16, and registers 18 and 20. Thus most of the input and/or output lines are synchronized to the clock line signal. Therefore this is a synchronous SRAM.
For such synchronous SRAMs, the input lines (such as the address or control lines) must be stable, i.e. in a ready state, prior to the occurrence of a rising edge of the clock signal. This is because the rising edge of a clock signal causes the various registers to sample the values of the connected input lines. The finite time that the input lines are stable before the clock transition is called the setup time. Similarly, the input lines need to be stable for a finite time immediately after the occurrence of a rising edge of the clock signal. This second finite time is called the hold time. The setup time t.sub.S and hold time t.sub.H are illustrated in FIG. 2. The time periods prior to the setup time t.sub.S, and following the hold time t.sub.H, are labelled as "don't care", i.e. the state of the lines is not important. The clock signal rising edge is also indicated in FIG. 2.
One way to implement the input register so as to properly sample the inputs within the setup time and hold time constraints at the rising edge of the clock signal is a master-slave combination of latches, of the type shown in FIG. 3, including conventional master-slave D-type flip-flop register 30 which includes a master latch and a slave latch. Register 30 is timed by the clock signal provided at node 32 which is buffered by a TTL buffer 34. The data input to the register 30 is provided at input node 36 via TTL buffer 38. The output of register 30 is provided on line 40 at the Q output thereof.
For many applications the hold time t.sub.H is either 0 (measured in nanoseconds) or a very small time duration (such as 0.5 or 1 nanosecond). The delay due to the TTL buffer 38 in FIG. 3 may be shorter than the delay due to the TTL buffer 34 of the clock line under certain conditions (voltage, temperature, input transition and/or process variations).
In order to guarantee the hold time specification (for example 0.5 nanosecond) at the input register, it is necessary to compensate for the delay difference between TTL buffer 38 and TTL buffer 34 in FIG. 3 by including additional delay between the input line node 36 and the D terminal of register 30 of FIG. 3. Thus the correct data signal is sampled upon transition of the clock signal at node 32, even though the input line at node 32 changes its value immediately after the hold time delay. Note that this delay could be zero if the hold time is equal to zero.
Such additional needed delay is shown in FIG. 4 including additional delay elements (buffers) 42. Otherwise, FIG. 4 is similar to FIG. 3.
For a synchronous circuit, the access time from the clock rising edge to occurrence of a valid output data signal is a key parameter referred to as the clock to data output time (t.sub.cd). A small clock to data output time is highly desirable for synchronous memory or synchronous logic performance. Any reduction of logic function between input register and output pad or between input register and the next register will reduce clock-to-data output delay.
FIG. 5 depicts circuitry additional to that of FIG. 4, including a master-slave register 50 having a D data input and a C clock input. In this case the clock signal input at node 52 is, as before, supplied via a buffer 54 to the clock input terminal C of register 50. Here there are two data input nodes, designated A0 (reference number 56) and A1 (reference number 58) each with an associated buffer 60, 62. Each input node 56, 58, is associated respectively with a register 50, 64. The outputs of registers 50 and 64 are provided to, in this case, NAND gate 66 and inverter 68 which together provide additional logic functions. Downstream of these additional logic functions are connected conventional inverters 70, 72. Each input node 56 and 58 has delay elements 76, 78 connected between it and the D input of the respective registers 50 and 64. Thus, in this case the SRAM input registers have associated logic functions for combining various inputs, for instance for address decoding.
It would be highly desirable to improve the performance of the circuit of FIG. 5 so as to allow faster functioning, i.e. less clock-to-data output delay.